1. Field of the Invention
The present invention relates to an intelligent PC add-in board and particularly to such an intelligent PC add-in board to provide a high speed access to a program memory and a data memory via an access route such as a bus.
2. Description of Prior Art
As a board for adding the above-described desired function, for example, to form a disk array system by being mounted to a system bus on PC (personal computer) or server for connection with a disk in the host system or an external disk, an intelligent PC add-in board is in the Art. Such an intelligent PC add-in board comprises a firm CPU for alleviating load of the host CPU.
The existing intelligent PC add-in board 21 of the related art is provided, is disposed in the same physical area, with a program memory 22 which stores the desired programs, and a data memory 23 which stores various data through data transfer process between host system (not illustrated) and external connecting devices, as illustrated in FIG. 3. The program memory 22 is connected with the firm CPU for executing the control process conforming to such program using the CPU local bus 25 as the address path.
Moreover, the firm CPU 24 is connected with a connecting device controller 26 to interface with an external connecting device (such as a scanner and printer or the like) by controlling SCSI and LAN, IO, etc. depending on the control instruction of this firm CPU24 using the CPU local bus 25 as the address path. The SCSI controller 26a and LAN controller 26b or IO controller 26c may be used as the connecting device controller 26. These connecting device controllers 26 are also connected with the data memory 23 via the CPU local bus 25, to provide access thereto.
Moreover, the CPU local bus 25 is connected with a primary bus/CPU local bus controller 28 for controlling transmission and reception of data between buses. This primary bus /CPU local bus controller 28 is connected with the primary PCI bus 29. This primary PCI bus 29 can be connected with a host system (not illustrated) and these CPU local bus 25, primary bus/CPU local bus controller 28 and primary PCI bus 29 form the access path.
That is, the host CPU (not illustrated) of the host system, program memory 22 and data memory 23 are respectively connected and the program execution instruction for the firm CPU 24 and parameters or the like are transmitted to the program memory 22 from the host CPU and data transfer process is executed for the data memory 23. In addition, the host memory (not illustrated) of the host system and firm CPU 24 are connected and the firm CPU 24 can read the program execution instruction on the host memory.
According to the intelligent PC add-in board 21 of the related art explained above, when the host system issues the program execution instruction to the firm CPU 24, this program execution instruction is transferred to the CPU local bus 25 from the primary PCI bus 29 under the control of the primary bus/CPU local bus controller 28 and is then transmitted to the program memory 22. The program execution instruction is read by the firm CPU 24 to execute the program. Alternatively, the firm CPU 24 reads the program execution instruction on the host CPU to execute it depending on the access path of the CPU local bus 25, primary bus/CPU local bus controller 28 and primary PCI bus 29.
For example, when the program execution instruction for the firm CPU 24 is a command to control the SCSI controller 26a, etc., the firm CPU 24 provides access to the connecting device controller 26 via the CPU local bus 25 to generate the control instruction and thereby the connecting device controller 26 controls an external connecting device.
Moreover, when the host CPU of the host system provides data-access to the data memory 23, the data transfer is performed between the primary PCI bus 29 and CPU local bus 25 under the control of the primary bus/CPU local bus controller 28 in order to execute the process.
In addition, when the external connecting device provides data-access to the data memory 23, the data transfer process is performed with the data memory 23 via the connecting device controller 26 and CPU local bus 25.
As explained above, the intelligent PC add-in board 21 of the related art has shared a part of the role of host CPU and host memory of the host system to realize effective control process by receiving an instruction of the host system with the firm CPU 24 or executing, independent of such instruction, the program in the program memory 22 or storing, in the data memory 23, the access data transmitted and received between the host system and external connecting device.
However, the intelligent PC add-in board 21 of the related art has a problem that when the program process by the firm CPU 24 is overlapped in time with the data access process from the host system and external connecting device, each processing time is reduced. This results in slower processing rate because the program memory 22 and the data memory 23 exist in the same storing area from the physical viewpoint.
In addition, transmission and reception of data to the data memory 23 from the host system are conducted via the CPU local bus 25 from the primary PCI bus 29 and on the other hand, transmission and reception of data to the data memory 23 from the SCSI controllers 2/6a, etc. are conducted via the CPU local bus 25 and such transmission and reception are performed finally using the same CPU local bus Therefore, when data access is made at the same time to the data memory 23 from both elements, there problem arises that any one access is placed in the waiting condition. This results in bad processing efficiency.
Due to these problems explained above, a part of the processing time has been wasted uselessly, as illustrated in FIG. 4, because the program process by the firm CPU 24, data access process by the connecting device controller 26 and data access process by the host system have inevitably been placed in the waiting condition until the other processes are completed.
It is therefore an object of the present invention to provide an intelligent PC add-in board which enables respectively the program execution process and data transfer process at a high speed and also improves the processing rate by effectively conducting the data transfer process between the host system, external connecting device and data memory.
It is another object of the present invention that since the program memory and data memory are provided in different areas because the data memory is respectively provided with the path with which the host system provides access via the primary bus and the path with which the external connecting device provides access via the secondary bus. The program memory and data memory are separated and the program process for providing access to the program memory and the data transfer process for providing access to the data memory can be realized independently even if these are overlapped in the time. Thereby, a high speed process can be realized and two independent access paths to the data memory can also be established to assure effective and high speed response to respective data access.
It is further object of the present invention that the data memory controller for controlling access to the data memory from the primary bus and secondary bus comprises a buffer and additionally the primary bus controller has a buffer to tentatively store the access data between the data memory controller and primary bus and the secondary bus controller has a buffer to tentatively store the access data between the data memory controller and secondary bus. Even if the read/write access from the primary bus and the read/write access from the secondary bus are generated in the same time, each buffer can tentatively store the data at order to continue without any delay the data process in the host system and external connecting device in order to assure the effective and high speed response.